This project is a prototype of Traffic light system where lights (Red, Yellow, Green) changes its state when timer becomes zero. Traffic lights operate with the rising edge of the clock. Clock pulse is generated by using a 50 MHz on board crystal. Its working is similar to Normal traffic lights. But single CPLD chip can be used to control the traffic of number of road signals. Because it has large number of inputs and outputs pin. In its working +5V is given to the CPLD and as it receive the rising edge of clock, and it starts its sequence of traffic lights. We can increase or decrease the delay between the transitions of signals according to the requirement. It reduces the complexity and has number of advantages of using CPLD instead of microcontroller.
Device Control, ASIC, CPLD, FPGA, Chip Designing, multiplying circuits, Automation, Featured Projects, Starred Projects, Exciting Projects, VLSI, Verilog, VHDL, Very Large Scale Integration, IC Fabrication, Logic Gates, Digital Signal Processing Chips